1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to a memory cell layout of a static random access memory (SRAM) within a semiconductor memory device that supports two data ports.
2. Description
Semiconductor memory devices can be classified as dynamic random access memories (DRAMs) and static random access memories (SRAMs) based on the memory system. SRAMs have the advantages of high speed, low power consumption, and simpler operation. In addition, an SRAM does not require periodically refreshing information that is stored and is compatible with the manufacturing process of a logic semiconductor device. Thus, the SRAM has been widely used in embedded memory devices.
A memory cell of an SRAM includes two drive transistors or pull-down transistors, two load modules, and two pass transistors or access transistors. SRAMs can be classified as CMOS SRAMs, high load resistor (HLR) SRAMs, or thin film transistor (TFT) SRAMs, based on the type of the load module. A CMOS SRAM uses a P-channel type field effect (PMOS) transistor as the load module, an HLR SRAM uses a high load resistor as the load module, and a TFT SRAM uses a polysilicon thin film transistor as the load module.
Thus, a memory cell of a CMOS SRAM has a total six of transistors, including two PMOS transistors that are used as the load module. In general, among the six transistors, four transistors are N-channel type field effect (NMOS) transistors; two driving NMOS transistors and the two PMOS transistor constitute two inverters, and the remaining two NMOS transistors are pass transistors.
There are many factors which restrict the operating speed of the CMOS SRAM. For example, the operating speed of the CMOS SRAM is affected by resistance related characteristics of SRAM wiring lines, the magnitude of parasitic capacitance occurring between bit lines and complementary bit lines adjacent to the bit lines, the number of ports serving as paths for reading and writing data, and the like.
In general, a CMOS SRAM with six transistors supports a single port. That is, a pair composed of a bit line and a complementary bit line is connected to a node through two pass transistors, the node corresponding to memory that includes two inverters. For example, Japanese Patent Publication No. Hei 10-178110 discloses an equivalent circuit of a single port SRAM having six transistors and a memory cell layout that includes the equivalent circuit.
The single port SRAM uses the pair of the bit line and the complementary bit line (hereinafter, referred to as a pair of bit lines) as an input/output node. Thus, the single port SRAM cannot input and output data at the same time. Therefore, the extent to which operating speed can be improved in the single-port SRAM is limited.
In order to improve the operating speed of a CMOS SRAM, a multi-port CMOS SRAM has been suggested. A multi-port CMOS SDRAM includes a plurality of input nodes and/or output nodes. In general, more than seven transistors are included in a memory cell of multi-port COMS SRAM. However, more than ten transistors may be included under certain conditions.
A multi-port CMOS SRAM can simultaneously read and write data through both ports, i.e., the input port and the output port. While data is read from a memory cell in the single port CMOS SRAM, data cannot be written to another memory cell if the memory cells are connected to the same pair of bit lines. Thus a delay time occurs between data write and read operations. In contrast to the single port CMOS SRAM, a multi-port CMOS SRAM can read data from a memory cell while writing data to another memory cell, even if the memory cells are connected to the same pair of bit lines. Thus, a delay does not occur between a data write operation and a data read operation.
In order to achieve higher speeds of operation than achieved in the past in a multi-port CMOS SRAM, various proposals of equivalent circuits and arrangements of devices constituting the equivalent circuits have been suggested. Typically, each device is arranged to adapt to a system's required performance. As described above, since an SRAM consumes little power and operates at a high speed, each device is arranged such that both of these two characteristics, i.e. low power consumption and high operating speed, are achieved, or one of the two characteristics is fully achieved.
U.S. Pat. No. 6,347,062 discloses a diagram of an equivalent circuit of a memory cell of multi-port CMOS SRAM and a layout of a memory cell of a multi-port CMOS SRAM. FIGS. 1 and 2 respectively show the diagram of the equivalent circuit and the diagram of the layout according to U.S. Pat. No. 6,347,062. The equivalent circuit of FIG. 1 corresponds to a CMOS SRAM that supports two ports. Reference numerals presented in FIGS. 1 and 2 represent the same as those disclosed in U.S. Pat. No. 6,347,062.
Referring to the SRAM supporting two ports (dual port SRAM) in FIG. 1 according to the prior art, a first P-channel type MOS transistor P1 and a first N-channel type MOS transistor N1 constitute a first CMOS inverter. A second PMOS transistor P2 and a second NMOS transistor N2 constitute a second CMOS inverter. Input nodes and output nodes of these CMOS inverters are cross connected at a first memory node MA and a second memory node MB. Thus these CMOS inverters constitute a flip-flop circuit.
A third NMOS transistor N3 and a fourth NMOS transistor N4 are pass transistors that function as access transistors. Gates of the pass transistors N3 and N4 are connected to a first word line WWL. Source regions and drain regions of the pass transistor N3 and N4 are connected to the memory nodes MA and MB, respectively, and a pair of first bit lines WBL1 and WBL2.
A fifth NMOS transistor N8 and a sixth NMOS transistor N9 are scan transistors. The scan transistors N8 and N9, along with a second bit line RBL and a second word line RWL, which are connected to the scan transistors N8 and N9, function as a second output port. The fifth NMOS transistor N8 has a gate connected to the first memory node MA, a source region connected to a ground voltage, and a drain region connected to the source region of the sixth NMOS transistor N9. The sixth NMOS transistor N9 has a gate connected to a second word line RWL, and a drain region connected to a second bit line RBL.
According to the equivalent circuit described, it is possible to read and write data through the first port using the first word line WWL and the pair of first bit lines WBL1 and WBL2. In addition, it is possible to read data through the second port using the second word line RWL and the second bit line RBL. In particular, regardless of whether the first port operates or not, it is possible to separately read data through the second port.
The layout of the memory cell having the equivalent circuit of FIG. 1 can be represented in various ways. The performance of a semiconductor memory device can also vary with respect to the layout of the memory cell. FIG. 2 shows a layer of a multi-layered layout of the dual-port SRAM of FIG. 1.
As shown in the dual-port SRAM of FIG. 2 according to the prior art, each unit memory cell is formed on a semiconductor substrate. Each unit memory cell can include an N-well area NW and two P-well areas, i.e., a first P-well area PW1 and a second P-well area PW2, which are disposed separately on the two sides of the N-well area NW. That is, the first PMOS transistor P1 and the second PMOS transistor P2 can be formed in the N-well area NW. The first NMOS transistor N1 and the third NMOS transistor N3 are formed in the first P-well area PW1. The second NMOS transistor N2, the fourth NMOS transistor N4, the fifth NMOS transistor N8, and the sixth NMOS transistor N9 are formed in the second P-well area PW2.
According to such a layout, it is possible to form the pair of first bit lines WBL1 and WBL2, and the second bit line RBL in parallel to the boundary between the N-well area NW and the first P-well area PW1 and the boundary between the N-well area NW and the second P-well area PW2.
Therefore, according to prior art, it is possible to manufacture an SRAM with higher speeds of operation by shortening the first lines WBL1 and WBL2, and the second bit line RBL.
However, in such a layout, since two P-well areas PW1 and PW2 are disposed separately on the two sides of the N-well area NW, boundaries between well areas become long. As a result, an isolation area is formed on the boundaries to separate the wells from one another, thus occupying a large amount of area and increasing the area per unit memory cell.
Accordingly, it would be desirable to provide a semiconductor memory device which is capable of simultaneously reading and writing data through two ports, and consists of a reduced isolation area that is formed on a boundary by producing a layout of memory cell elements with more effective wiring and reducing the boundary between an N-well area and a P-well area.
It would also be desirable to provide a semiconductor memory device achieving superior performance by removing unnecessary wiring elements and effectively arranging wiring lines.
According to one aspect of the present invention, there is provided a dual-port semiconductor memory device comprising a semiconductor substrate, which includes a memory cell having one N-well area where a p+-type active region is formed and one contiguous P-well area where an n+-type active region is formed, a first word line, a second word line (scan address line), a first bit line, a first complementary bit line, a second bit line (scan data out line), a first CMOS inverter, which includes a first NMOS transistor, a first PMOS transistor, an input terminal, and an output terminal, a second CMOS inverter, which includes a second NMOS transistor, a second PMOS transistor, an input terminal, and an output terminal, wherein the input terminal of the second CMOS inverter is connected to the output terminal of the first CMOS inverter to form a first memory node and the output terminal of the second CMOS inverter is connected to the input terminal of the first CMOS inverter to form a second memory node, a third NMOS transistor, which has a gate connected to the first word line, a drain connected to the first bit line, and a source connected to the first memory node, a fourth NMOS transistor, which has a gate connected to the first word line, a drain connected to the first complementary bit line, and a source connected to the second memory node, a fifth NMOS transistor, which has a gate connected to the first memory node and a source connected to a ground line, and a sixth NMOS transistor, which has a gate connected to the second word line, a source connected to the drain of the fifth NMOS transistor, and a drain connected to the second bit line. The first PMOS transistor and the second PMOS transistor are disposed in the p+-type active region of the N-well area; and the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are formed in the n+-type active region of the contiguous P-well area.
According to another aspect of the present invention, there is provided a dual-port semiconductor memory device comprising a semiconductor substrate, which includes a memory cell having one N-well area where a p+-type active region is formed and one contiguous P-well area where an n+-type active region is formed, a first word line, a second word line (scan address line), a first bit line, a first complementary bit line, a second bit line (scan data out line), a first CMOS inverter, which includes a first NMOS transistor, a first PMOS transistor, an input terminal, and an output terminal, a second CMOS inverter, which includes a second NMOS transistor, a second PMOS transistor, an input terminal, and an output terminal, wherein the input terminal of the second CMOS inverter is connected to the output terminal of the first CMOS inverter to form a first memory node and the output terminal of the second CMOS inverter is connected to the input terminal of the first CMOS inverter to form a second memory node, a third NMOS transistor, which has a gate connected to the first word line, a drain connected to the first bit line, and a source connected to the first memory node, a fourth NMOS transistor, which has a gate connected to the first word line, a drain connected to the first complementary bit line, and a source connected to the second memory node, and a fifth NMOS transistor, which has a gate connected to the second word line, a source connected to the first memory node, and a drain connected to the second bit line. The first PMOS transistor and the second PMOS transistor are disposed in the p+-type active region of the N-well area; and the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor are formed in the n+-type active region of the contiguous P-well area.
Beneficially, the N-well area is disposed at a corner of the memory cell, and the contiguous P-well area is disposed in a remaining portion of the memory cell.
Beneficially, a plurality of N-well areas constitute a separate N-well area, which is surrounded by the contiguous P-well area, and the dual-port semiconductor memory device further comprises a well contact used to connect the one separate N-well area with a power source of the semiconductor memory device.
Beneficially, a second n+-type active region, which is connected to the well contact, is further formed in the p+-type active region of the separate N-well area, and a silicide layer is formed in the second n+-type active region and the p+-type active region to connect the second n+-type active region and the p+-type active region to each other. It is beneficial that the one separate N-well area is shared by four memory cells.
Beneficially, the n+-type active region and the well contact in the p+-type active region are shared by two memory cells adjacent to each other.
Beneficially, an N-well bridge is further formed in the contiguous P-well area to connect the N-well areas of the memory cells adjacent to each other. Beneficially, a width of the N-well bridge is 10% to 50% of a width of the N-well area.
Beneficially, the second word line is parallel to the first word line.
Beneficially, the second bit line is parallel to the first bit line.